Embodiments of the present invention relate to a nonvolatile memory device and a method of programming the same.
In a nonvolatile memory device, a program operation is performed by supplying a ground voltage (e.g., 0 V) to a bit line coupled to a selected memory cell and a program voltage to a corresponding word line.
The states of the threshold voltages of single level cells (SLCs) are divided into an erase state and a program state. The states of the threshold voltages of multi-level cells (MLCs) include a number of periods. Accordingly, it is desirable to secure the margin between the threshold voltages. The reason for its desirability is described in more detail with reference to the drawings.
FIG. 1 is a circuit diagram of a conventional nonvolatile memory device.
The nonvolatile memory device includes a memory cell array 10, a row decoder 20 configured to output a driving voltage to word lines WL0 to WLn, and a page buffer unit 30 configured to temporarily store data when a program operation, a verification operation, or a read operation is being performed.
The memory cell array 10 can include a number of memory blocks. Only one memory block is shown in FIG. 1, for convenience of description. The memory block includes a number of strings ST1 to STk. Each of the strings includes memory cells F0 to Fn coupled together in series, and a drain select transistor DST and a source select transistor SST respectively coupled to the ends of the memory cells F0 to Fn. The gate of the drain select transistor DST is coupled to a drain selection line DSL, and the gate of the source select transistor SST is coupled to a source selection line SSL. Furthermore, the gates of the memory cells F0 to Fn are respectively coupled to the word lines WL0 to WLn. The source of the source select transistor SST is electrically coupled to a common source line CSL. The drains of a pair of the drain select transistors DST are coupled to respective bit lines BLe and BLo.
The row decoder 20 is configured to output a driving voltage to the drain selection line DSL, the source selection line SSL, and the word lines WL0 to WLn.
The page buffer unit 30 includes a number of page buffers. Each of the page buffers can be coupled to an even bit line BLe and an odd bit line BLo, or two page buffers can be coupled to the even and odd bit lines BLe and BLo, respectively.
An operation of programming the nonvolatile memory device is briefly described below.
To perform the program operation, a power source voltage is supplied to a bit line coupled to an unselected string (i.e., a string not including memory cells to be programmed), a ground voltage (e.g., 0 V) is supplied to a bit line coupled to a selected string (i.e., a string including memory cells to be programmed), a pass voltage is supplied to an unselected word line, and a program voltage is supplied to a selected word line.
In particular, a voltage supplied to the word lines WL0 to WLn is output from the row decoder 20. Thus, the program voltage is supplied later to a string far away from the row decoder 20 than to a string close to the row decoder 20 because of a delay time. That is, in FIG. 1, the program voltage is supplied later to the strings of a region B than to the strings of a region A. Furthermore, the program voltage is supplied later to the strings of a region C than to the strings of the region B. The reason is described in more detail below with reference to FIG. 2.
FIG. 2 is a graph showing a conventional program period.
A program voltage is output from the row decoder 20. Thus, the time during which the program voltage is supplied to memory cells close to the row decoder 20 is long (refer to A of FIG. 2), and the time during which the program voltage is supplied to memory cells far away from the row decoder 20 is short (refer to C of FIG. 2). Such a phenomenon is caused by the time that the program voltage takes to reach corresponding memory cells from the row decoder 20 (i.e., a delay time). The time when the program voltage is supplied to a selected word line is the same, but the time that the program voltage takes to reach each memory cell coupled to the selected word line differs depending on the distance therebetween. Accordingly, the time when each memory cell is programmed also differs. Consequently, the threshold voltages of the memory cells can differ.
FIG. 3 is a graph showing conventional distributions of threshold voltages.
Although memory cells are supplied with program voltages having the same level, they can have different threshold voltages because of a difference in the time period during which the program voltage is being supplied. In FIG. 3, a graph C shows a distribution of the threshold voltages of the memory cells coupled to the strings belonging to the region C shown in FIG. 1. A graph B shows a distribution of the threshold voltages of the memory cells coupled to the strings belonging to the region B shown in FIG. 1. A graph A shows a distribution of the threshold voltages of the memory cells coupled to the strings belonging to the region A shown in FIG. 1. That is, a distribution of the threshold voltages of memory cells coupled to strings far away from the row decoder 20 (refer to FIG. 1) can be lower than a distribution of the threshold voltages of memory cells coupled to strings close to the row decoder 20 (refer to FIG. 1).
In this case, if the memory cells have different threshold voltages, although the same program operation is performed on the memory cells, the reliability of a nonvolatile memory device can be deteriorated.